Regviz

Microchip Technology /ATSAMD21J17A /SYSCTRL /DFLLCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DFLLCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMD21J17A/SYSCTRL/DFLLCTRL#0x0

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0 (MODE)MODE 0 (STABLE)STABLE 0 (LLAW)LLAW 0 (USBCRM)USBCRM 0 (RUNSTDBY)RUNSTDBY 0 (ONDEMAND)ONDEMAND 0 (CCDIS)CCDIS 0 (QLDIS)QLDIS 0 (BPLCKC)BPLCKC 0 (WAITLOCK)WAITLOCK

Description

DFLL48M Control

Fields

ENABLE

DFLL Enable
MODE

Operating Mode Selection
STABLE

Stable DFLL Frequency
LLAW

Lose Lock After Wake
USBCRM

USB Clock Recovery Mode
RUNSTDBY

Run in Standby
ONDEMAND

On Demand Control
CCDIS

Chill Cycle Disable
QLDIS

Quick Lock Disable
BPLCKC

Bypass Coarse Lock
WAITLOCK

Wait Lock

Links

()

Register License

Copyright © 2018 Microchip Technology Inc.

SPDX-License-Identifier: Apache-2.0

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data